Join Capgemini Engineering as a VLSI DFT Architect and lead critical Design-for-Test execution across complex IP and SoC programs. You will be instrumental from architecture definition through to silicon production, ensuring robust test solutions for cutting-edge semiconductor and technology companies.

This role offers exposure to the complete silicon lifecycle, working on advanced ASIC, SoC, AI, Automotive, Networking, and HPC projects. You will collaborate with globally distributed engineering teams and have access to continuous learning and upskilling opportunities.

We are seeking experienced professionals with a proven track record in end-to-end DFT implementation for successful SoC tape-outs. If you are passionate about driving technical excellence and shaping the future of DFT methodologies, this is your opportunity.

Lead DFT execution for IP and SoC programs, from architecture to silicon production. Define and implement Scan, Scan Compression (EDT), ATPG, MBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG) solutions. Drive scan insertion, DFT integration, and sign-off using industry-standard EDA tools. Generate and optimize ATPG patterns to achieve high fault coverage and production test goals. Perform DFT DRC checks, coverage analysis, and debug scan, compression, and ATPG issues. Develop and validate STA constraints for various test modes. Support silicon bring-up, failure diagnosis, yield improvement, and production ramp activities. Collaborate with cross-functional teams to resolve test-related challenges. Develop automation solutions using TCL, Perl, Python, and Shell scripting. Mentor junior engineers and contribute to DFT methodology improvements.

15 to 20+ years of hands-on experience in Design-for-Test (DFT) for ASIC and SoC development. Proven experience leading end-to-end DFT implementation for multiple successful SoC tape-outs. Strong expertise in Scan Insertion, Scan Compression (EDT), ATPG, MBIST, LBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG). Hands-on experience with Synopsys TestMAX/DFTMAX, TetraMAX, Fusion Compiler, Siemens Tessent Suite, or Cadence Modus tools. Deep understanding of fault models (Stuck-at, Transition, Path Delay, Bridge Fault, Cell-Aware ATPG). Experience in DFT verification, DRC closure, ATPG pattern validation, and fault coverage optimization. Strong knowledge of timing constraints, STA for test modes, clocking architectures, and low-power DFT. Experience supporting silicon bring-up, tester debug, diagnosis, yield improvement, and production ramp. Proficiency in TCL, Perl, Python, and Shell scripting for automation.