Join NVIDIA as a Senior Verification Engineer and play a pivotal role in shaping the future of PCI Express controllers for cutting-edge GPUs and SOCs. This is a unique opportunity to contribute to groundbreaking products that span consumer graphics, autonomous vehicles, and the rapidly expanding field of artificial intelligence. Become part of a global team dedicated to pushing technological boundaries and defining the next era of computing, where passion for parallel and visual computing drives innovation.

NVIDIA's GPUs have evolved from powering immersive virtual worlds to simulating human intelligence, forming the core of advanced AI systems. As the "AI computing company," NVIDIA is at the forefront of developing intelligent machines, robots, and self-driving cars that understand and interact with their environment.

We foster an environment where creativity, autonomy, and a passion for challenges are highly valued. As an equal opportunity employer, we celebrate diversity and are committed to creating an inclusive workplace.

Take ownership of the verification process for ASIC designs, architectures, golden models, and micro-architectures of PCI Express controllers at both IP and sub-system levels, utilizing advanced methodologies like UVM.

Develop robust, reusable bus functional models, monitors, checkers, and scoreboards, adhering to coverage-driven verification principles.

Deeply understand design specifications and implementations to define verification scope, craft comprehensive test plans and tests, and build the necessary verification infrastructure to ensure design correctness.

Collaborate closely with architects, designers, and pre and post-silicon verification teams to achieve project objectives.

Possess a B.Tech./M.Tech or equivalent experience, coupled with a minimum of 2 years of relevant professional experience.

Demonstrate proficiency in verification at Unit, Sub-system, or SOC levels, with strong expertise in Verilog and SystemVerilog.

Exhibit comprehensive verification expertise in IP or interconnect protocols such as PCI Express, USB, or SATA.

Showcase experience in developing and operating within functional coverage-based constrained random verification environments.

Familiarity with DV methodologies like UVM/VMM and exposure to industry-standard simulation and debug tools are essential.

Stand out with excellent knowledge of PCI Express protocols (Gen3 and above) and a solid understanding of system-level architectures for PCIE/CXL-based designs. Experience with scripting languages like Perl or Python, along with strong debugging, analytical, and interpersonal skills, are highly desirable.