NVIDIA is seeking imaginative individuals to join its networking group, contributing to the advancement of datacenter chips and systems. This role offers direct experience with high-performance queuing and scheduling sub-systems, driving the future of technology.

As a key member of the team, you'll be instrumental in crafting cutting-edge solutions that define the next era of computing. Your work will directly impact the performance and capabilities of our advanced hardware.

Join a diverse and supportive environment where innovation thrives. NVIDIA fosters a culture of collaboration, empowering its employees to achieve their best and make a lasting global impact.

Develop verification components and APIs for unit and cluster-level test benches, specifically verifying queuing and scheduling algorithms and designs.

Architect testbenches and verification environments using Specman, defining test plans and verification infrastructure for clusters and systems.

Build efficient, reusable bus functional models, monitors, checkers, and scoreboards, implementing functional coverage and ensuring unit/cluster-level verification closure. Collaborate with architects, designers, FPGA, and post-silicon teams to guarantee unit robustness.

A B.Tech or M.Tech in ECE, EE, CSE, or an equivalent degree is required, coupled with over 3 years of experience in verification closure of complex units, sub-systems, or SOC levels.

Proven expertise in networking Datapath and Switching verification IPs is essential. Familiarity with modern verification methodologies like SV and UVM is beneficial.

Strong debugging and analytical skills, proficiency with industry-standard verification tools for simulation and debug, and excellent interpersonal and communication abilities for global team collaboration are expected.