Join NVIDIA, a leader in transforming computer graphics, PC gaming, and accelerated computing for over 25 years. We are pioneering the next era of computing with AI, where our GPUs power intelligent systems. Our supportive and diverse environment inspires groundbreaking work. We are seeking enthusiastic individuals for our networking group to contribute to the future of datacenter chips and systems, gaining direct experience with high-performance queuing and scheduling sub-systems.

Develop verification components and APIs for unit and cluster-level test benches, focusing on queuing and scheduling algorithms. Architect testbenches and verification environments using Specman. Define test plans, tests, and verification infrastructure for clusters and systems. Build reusable bus functional models, monitors, checkers, and scoreboards. Implement functional coverage and ensure unit/cluster-level verification closure. Collaborate with architects, designers, FPGA, and post-silicon teams for unit robustness.

A B.Tech or M.Tech degree in ECE, EE, CSE, or an equivalent is required. Candidates must possess over 3 years of experience in verification closure for complex units, sub-systems, or SOC levels. Proven experience with networking-specific Datapath and Switching verification IPs is essential. Familiarity with the latest verification methodologies like SV and UVM is beneficial. Strong debugging and analytical skills, along with exposure to industry-standard simulation and debug tools, are necessary. Excellent interpersonal and communication skills are needed to collaborate effectively with global, cross-cultural teams.