Lead the performance verification group for NVIDIA's next-generation DPUs and SmartNICs. This pivotal role involves providing technical leadership and owning end-to-end pre-silicon performance signoff for the System on Chip (SoC). We seek an individual passionate about building high-performing teams, driving execution across multiple projects, and collaborating with architecture, microarchitecture, IP, SoC integration, and program management teams.

This position offers the opportunity to shape world-class silicon by fostering innovation and ensuring peak performance. You will be instrumental in defining the future of networking hardware at NVIDIA.

Manage and mentor a team of verification engineers, establishing team structure, hiring plans, and career development. Drive the performance verification strategy for sophisticated NIC designs, working closely with design and architecture teams to address performance bottlenecks. Develop and implement reusable testbench infrastructure and targeted test scenarios for full-chip NIC performance verification, utilizing a deep understanding of NIC microarchitecture and traffic flows. Build robust infrastructure and tooling for efficient performance debugging.

Create detailed performance test plans for next-generation features. Employ advanced verification methodologies and tools like Specman/e and SystemVerilog/UVM. Enhance design and verification methodologies and best practices. Integrate AI workflows to boost team productivity and design quality.

A Bachelor's or Master's degree in Electrical Engineering or Computer Engineering, or equivalent experience is required. A minimum of 10 years in ASIC/SoC verification, with at least 3 years in people management or technical leadership, is essential. Strong expertise in verification methodologies (UVM, constrained-random, coverage-driven) and digital design fundamentals (RTL, architecture, microarchitecture, power analysis) is crucial.

Proven ability to manage SoC teams while balancing resources, schedules, and quality. Experience with EDA simulation and debugging tools is necessary. Excellent communication skills to articulate technical status, risks, and trade-offs to leadership and cross-functional partners are vital. Experience verifying complex designs' performance, networking domains, or building scalable verification infrastructure is advantageous.