Join a forward-thinking team dedicated to developing custom silicon solutions that will power Google's future direct-to-consumer products. You'll be instrumental in shaping next-generation hardware, driving unparalleled performance, efficiency, and integration for innovations used by millions globally.

This role is part of a dynamic Research and Development group. You will focus on building robust verification components, implementing constrained-random testing strategies, and conducting system-level testing to ensure comprehensive verification closure. Your work will involve verifying digital designs, close collaboration with design and verification engineers, and direct verification tasks.

The AI and Infrastructure team is at the forefront of technological advancement, empowering Google's customers with groundbreaking capabilities and insights. We deliver AI and Infrastructure at an unmatched scale, efficiency, reliability, and velocity. Our reach extends to Googlers, Google Cloud customers, and billions of users worldwide.

We are the engine behind Google's most significant innovations. Our teams enable the development of cutting-edge AI models, provide immense computing power for global services, and create the essential platforms for developers building the future. From software to hardware, we are shaping world-leading hyperscale computing, with key focuses on TPUs, Vertex AI for Google Cloud, Global Networking, Data Center operations, and systems research.

Plan the verification of digital design blocks by deeply understanding design specifications and collaborating with design engineers to pinpoint critical verification scenarios.

Develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or perform formal verification using SystemVerilog Assertions (SVA) and leading formal tools.

Identify and implement comprehensive coverage measures to capture corner-case scenarios effectively.

Debug tests collaboratively with design engineers to ensure the delivery of functionally accurate design blocks.

Achieve coverage closure to identify verification gaps and demonstrate progress towards tape-out.

A Bachelor's degree in Electrical Engineering or equivalent practical experience is required.

Possess 4 years of hands-on experience in creating and utilizing verification components and environments within standard verification methodologies.

Demonstrate experience in verifying digital logic at the RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering or a related discipline. Experience with UVM, comprehensive verification techniques, and the full verification lifecycle is highly valued. Familiarity with ASIC standard interfaces, memory system architecture, and performance verification of ASICs and their components is also beneficial.