Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology for Google's demanding AI/ML applications. Join a boundary-pushing team developing custom silicon solutions for Google's TPUs, contributing to innovations behind beloved products. Leverage your design and verification expertise with a focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team redefines possibilities, empowering Google customers with breakthrough capabilities at unparalleled scale and efficiency. Our work enables Googlers, Google Cloud customers, and billions of users worldwide. We are the driving force behind groundbreaking innovations, powering AI models, delivering computing power to global services, and providing platforms for developers.

Our teams shape world-leading hyperscale computing, from developing TPUs and Vertex AI for Google Cloud to managing Global Networking and Data Center operations. We are at the forefront of systems research and much more.

Define and document comprehensive DFT architecture for multi-core SoCs, incorporating strategies for hierarchical scan compression, extensive Memory BIST (MBIST), Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.

Lead the entire DFT lifecycle, from RTL planning to pattern handoff. Take ownership of schedules, resource allocation, and milestone tracking to ensure zero-defect delivery.

Implement next-generation DFT methodologies and automation flows to maximize test coverage while minimizing test time, pattern count, and silicon area overhead. Collaborate closely with post-silicon teams, Physical Design, and Power Architects.

Provide support during the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, guide vendor EDA tool selection and qualification, and serve as the primary technical liaison for DFT matters with stakeholders.

A Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience, is required.

Possess at least 10 years of experience in SoC DFT architecture and design. This includes extensive experience with critical DFT protocols such as Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

Demonstrate 10 years of experience utilizing industry-standard EDA tools like Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus. Additionally, you should have 4 years of people management experience, focusing on employee development and leading multiple SoC projects from RTL architecture through post-silicon validation.

Proficiency in Tcl, Python, or Perl for developing automation flows is essential.