Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology at Google Cloud. This role offers a unique opportunity to develop custom silicon solutions powering Google's most demanding AI/ML applications. Join a pioneering team that is redefining possibilities in AI and Infrastructure, empowering Google customers with scalable, efficient, and reliable breakthrough capabilities.

Our AI and Infrastructure team is at the forefront of innovation, enabling groundbreaking AI models and providing unparalleled computing power. We deliver essential platforms that allow developers to build the future, contributing to world-leading hyperscale computing. Our work encompasses TPUs, Vertex AI for Google Cloud, Google Global Networking, and Data Center operations, among other critical areas.

Define and document comprehensive DFT architectures for multi-core SoCs, encompassing scan compression, Memory BIST, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE networks. Lead the entire DFT lifecycle from RTL planning to pattern handoff, managing schedules, resources, and milestones for zero-defect delivery.

Deploy advanced DFT methodologies and automation to optimize test coverage while minimizing test time, pattern count, and silicon area. Collaborate closely with post-silicon teams, Physical Design, and Power Architects. Support the post-silicon phase through to Production Release Qualification (PRQ).

Mentor senior technical staff, lead vendor EDA tool selection and qualification, and serve as the primary technical liaison for DFT-related matters with all stakeholders.

Requires a Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience. Possess 10 years of experience in SoC DFT architecture and design, along with extensive experience in DFT protocols like Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

Demonstrate 10 years of proficiency with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus. Additionally, a minimum of 4 years of people management experience is essential, focusing on employee development and leading multiple SoC projects from RTL architecture through post-silicon validation.

Proficiency in Tcl, Python, or Perl for developing automation flows is a must. Preferred qualifications include a PhD in Electrical Engineering with a specialization in VLSI testing, fault tolerance, or reliability. Experience with advanced technology nodes, 2.5D/3D-IC packaging, high-speed I/O testing, managing global teams, and driving cross-functional timing/power analysis is highly advantageous.