Join Google Cloud and be at the forefront of AI/ML hardware acceleration. This role offers the chance to shape cutting-edge TPU technology that drives Google's demanding AI/ML applications. You will be part of a dynamic team dedicated to developing custom silicon solutions for the future of Google's TPUs. Leverage your extensive design and verification expertise to ensure the robust architecture and seamless integration of TPUs within AI/ML-driven systems. The AI and Infrastructure team is revolutionizing possibilities, empowering customers with unparalleled AI and Infrastructure capabilities at scale, efficiency, and reliability. We are the driving force behind Google's groundbreaking innovations, from cutting-edge AI models to the essential platforms enabling developers worldwide.

Define and document comprehensive DFT architectures for multi-core SoCs, encompassing strategies for hierarchical scan compression, Memory BIST (MBIST) for large memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks. Lead the entire DFT lifecycle from RTL planning to pattern handoff, managing schedules, resources, and milestones to achieve zero-defect delivery. Implement next-generation DFT methodologies and automation flows to maximize test coverage while minimizing test time, pattern count, and silicon area overhead. Collaborate closely with post-silicon teams, Physical Design, and Power Architects. Support the post-silicon phase for final Production Release Qualification (PRQ). Mentor senior technical staff, drive EDA tool selection and qualification, and serve as the primary technical liaison for DFT matters.

A Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience, is required. Candidates must possess 10 years of experience in SoC DFT architecture and design, along with 10 years of experience in critical DFT protocols such as Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687). Proficiency with industry-standard EDA tools like Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus is essential, spanning 10 years. Additionally, 4 years of people management experience, focusing on employee development and leading multiple SoC projects from RTL architecture through post-silicon validation, is necessary. Experience with automation flows using Tcl, Python, or Perl is also required. A PhD in Electrical Engineering with a specialization in VLSI testing, fault tolerance, or reliability is preferred. Experience with advanced technology nodes, 2.5D/3D-IC packaging, or high-speed I/O testing methodologies, as well as managing global technical teams and driving vendor engagement, is advantageous. The ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs is a plus.