Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology for Google's demanding AI/ML applications. Join a boundary-pushing team developing custom silicon solutions for Google's TPUs. Contribute to innovation behind globally loved products, leveraging design and verification expertise for complex digital designs, with a focus on TPU architecture and AI/ML systems.

The AI and Infrastructure team redefines possibilities, empowering Google customers with breakthrough capabilities and insights through unparalleled scale, efficiency, reliability, and velocity. Our reach extends to Googlers, Google Cloud customers, and billions of users worldwide.

We are the driving force behind Google's groundbreaking innovations, fueling AI model development, delivering superior computing power for global services, and providing essential platforms for developers. From software to hardware, our teams are shaping world-leading hyperscale computing, with key initiatives in TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Define and document comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for large memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.

Lead the entire DFT lifecycle from RTL planning to pattern handoff, managing schedules, resource allocation, and milestone tracking for zero-defect delivery.

Deploy next-generation DFT methodologies and automation flows to optimize test coverage while minimizing test time, pattern count, and silicon area overhead.

Collaborate effectively with post-silicon teams, Physical Design, and Power Architects.

Provide crucial support during the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, guide vendor EDA tool selection and qualification, and serve as the primary technical liaison for DFT matters with all stakeholders.

A Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience, is required.

Possess 10 years of experience in SoC DFT architecture and design, along with a decade of experience in DFT protocols such as Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

Demonstrate 10 years of proficiency with industry-standard EDA tools including Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.

Bring 4 years of people management experience, focusing on employee development and leading multiple SoC projects from RTL architecture through post-silicon validation.

Experience with scripting languages like Tcl, Python, or Perl for developing automation flows is essential.