Join Google Cloud's AI/ML hardware acceleration team and help define the future of technology. This role offers the chance to drive cutting-edge TPU development, powering Google's most advanced AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions. Contribute to innovations behind products used by millions and leverage your design and verification expertise within AI/ML-driven systems.

Define comprehensive DFT architecture for multi-core SoCs, including hierarchical scan compression, MBIST, Functional BISTs, Analog components, LBIST, high-speed I/O loopback, and JTAG networks. Lead the entire DFT lifecycle from RTL planning to pattern handoff, managing schedule, resources, and milestones for zero-defect delivery. Deploy advanced DFT methodologies and automation to maximize test coverage while minimizing test time and silicon area overhead.

Collaborate with post-silicon, Physical Design, and Power Architects. Support the post-silicon phase for Production Release Qualification (PRQ). Mentor senior technical staff, drive EDA tool selection/qualification, and serve as the primary technical liaison for DFT matters.

A Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience, is required. Candidates must have 10 years of experience in SoC DFT architecture and design, covering Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

Proficiency with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus is essential, along with 4 years of people management experience. Experience in Tcl, Python, or Perl for developing automation flows is also necessary.