Shape the future of AI/ML hardware acceleration and drive cutting-edge TPU technology that powers Google's most demanding AI/ML applications. Join a pioneering team dedicated to developing custom silicon solutions for Google's TPUs, contributing to innovations loved by millions. Leverage your design and verification expertise for complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining possibilities, empowering Google customers with breakthrough capabilities and insights through AI and Infrastructure at unparalleled scale, efficiency, and reliability. This team is the driving force behind Google's groundbreaking innovations, from cutting-edge AI models to essential platforms for developers, shaping the future of world-leading hyperscale computing.

Define and document comprehensive DFT architectures for multi-core SoCs, encompassing scan compression, Memory BIST (MBIST) for large memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.

Lead the entire DFT lifecycle from RTL planning to pattern handoff, taking ownership of schedules, resource allocation, and milestone tracking to ensure zero-defect delivery. Deploy next-generation DFT methodologies and automation flows to optimize test coverage, minimize test time, pattern count, and silicon area overhead.

Collaborate closely with post-silicon teams, Physical Design, and Power Architects. Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and serve as the primary technical liaison for DFT matters with stakeholders.

A Bachelor's degree in Electrical or Computer Engineering, or equivalent practical experience, is required, along with 10 years of experience in SoC DFT architecture and design. This includes extensive experience with DFT protocols such as Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

Proficiency with industry-standard EDA tools like Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus is essential. Additionally, 4 years of people management experience, including employee development and leading multiple SoC projects from RTL architecture through post-silicon validation, is necessary. Experience in Tcl, Python, or Perl for developing automation flows is also required.