Join a pioneering team crafting bespoke silicon solutions essential for Google's consumer products. You will be instrumental in advancing the innovation behind globally loved products. Your expertise will directly influence the next generation of hardware, delivering exceptional performance, efficiency, and seamless integration.

As a Silicon Validation Engineer on Google's Consumer Hardware Silicon team, you will develop high-performance, low-power hardware that fuels Google's ongoing innovation. You will be a vital contributor to the memory sub-system silicon validation team, ensuring the delivery of high-quality silicon to all internal clients, thereby enhancing customer experiences.

This role involves planning, creating, and executing tests to verify the functional integrity of System on Chips (SoCs) on both emulation and silicon platforms. You'll work under nominal and process, voltage, and temperature (PVT) conditions. Collaboration with cross-functional teams, including Silicon, Boards, Software, and Manufacturing, will be key for debugging failures. You will also measure and optimize silicon performance and power, enabling consistent and compelling use cases in our end products. Regular updates on silicon health will be provided to platform, software, and volume manufacturing teams.

Collaborate with Architecture, Design, and product teams to define memory subsystem validation requirements, including DDRPHY, Memory Controller, and DRAM.

Understand new designs and develop/execute validation tests on emulation platforms for tapeout, focusing on DDRPHY and DRAM subsystems.

Lead post-silicon bring-up and validation efforts for the DDRPHY/DRAM interface, encompassing tuning and characterization.

Develop a range of post-silicon validation, debug, and margin tools specifically for DDRPHY and DRAM.

Deliver consistent updates on emulation and silicon health to platform, software, and volume manufacturing teams.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience.

Four years of dedicated experience in silicon validation.

Proven experience with DDRPHY and DRAM tuning and characterization across PVT variations.

Demonstrated ability in developing test and debug infrastructure, including software tools, lab equipment, and test/lab automation scripting.

Expertise in low power DRAM interface protocols and their associated compliance.

Preferred qualifications include a Master's or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Familiarity with prototyping platforms like Emulators or FPGAs is beneficial, as is experience with power or performance measurement of SoCs. Proficiency in C/Python coding is also valued.