Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions that power our future direct-to-consumer products. You will play a crucial role in shaping next-generation hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions worldwide.

The AI and Infrastructure team is at the forefront of technological advancement, empowering Google customers with cutting-edge AI and infrastructure at an unprecedented scale. We enable groundbreaking AI models, deliver immense computing power for global services, and provide the foundational platforms for developers building the future. Our work spans software and hardware, with key contributions to TPUs, Vertex AI, Google Global Networking, and data center operations, defining the future of hyperscale computing.

Your key contributions will involve:

- Analyzing the instruction set and architecture of Machine Learning (ML) IPs, leading discussions on enhancements compared to previous generations. - Developing robust functional or performance models for ML IPs, integrating them with the Cloud TPU SoC model to establish a definitive architectural reference. - Collaborating closely with pre-silicon verification and post-silicon validation teams to seamlessly integrate models into their validation workflows. - Partnering with compiler and software teams to facilitate early development activities (left-shift).

Essential qualifications include:

- A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience. - Two years of experience in developing simulation models for hardware IPs, or holding a PhD. - Proven experience in developing software systems using modern C++.

Preferred qualifications:

- A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. - Demonstrated experience applying computer architecture principles to tackle complex, open-ended challenges. - Expertise in hardware and software co-design. - Familiarity with designing digital logic at the Register Transfer Level (RTL) using Verilog. - Understanding of processor design or accelerator designs, and the ability to map ML models to hardware architectures.