Join a forward-thinking team dedicated to crafting custom silicon that propels Google's direct-to-consumer products into the future. You will play a crucial role in innovating products enjoyed by millions globally, shaping next-generation hardware experiences for exceptional performance, efficiency, and integration.

The AI and Infrastructure team is at the forefront of innovation, delivering AI and Infrastructure at unmatched scale, efficiency, and reliability. We empower Google customers with cutting-edge capabilities and insights. Our reach extends to Googlers, Google Cloud clients, and billions of users worldwide.

We are the architects of Google's pioneering advancements. Our work drives the development of state-of-the-art AI models, provides immense computing power for global services, and establishes the foundational platforms for developers. From software to hardware, our teams are instrumental in defining the future of hyperscale computing, with significant contributions to TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Analyze the instruction set and architecture of Machine Learning (ML) Intellectual Property (IP) blocks, leading discussions on feature enhancements compared to the previous generation.

Develop functional or performance models for ML IPs. Integrate these functional models with the Cloud TPU System-on-Chip (SoC) model to establish a definitive architectural reference.

Collaborate with pre-silicon verification and post-silicon validation teams to implement the models within their respective validation workflows.

Partner with compiler and software development teams to facilitate early-stage development activities, enabling a "left-shift" approach.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline, or equivalent practical experience is required.

Possess 2 years of experience in developing simulation models for hardware IPs, or hold a PhD.

Demonstrated experience in developing software systems using modern C++ is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture.

Experience applying computer architecture principles to address complex, open-ended challenges is highly valued.

Familiarity with hardware and software co-design principles is beneficial.

Knowledge of Register Transfer Level (RTL) digital logic design using Verilog is desirable.

Understanding of processor design, accelerator designs, and the process of mapping ML models to hardware architectures is a plus.