Join a pioneering team developing advanced custom silicon solutions that will power the next generation of Google's direct-to-consumer products. You will play a crucial role in innovating hardware experiences, aiming for unparalleled performance, efficiency, and seamless integration. Our AI and Infrastructure team is at the forefront of innovation, enabling Google customers with groundbreaking capabilities and insights through AI and Infrastructure at an unprecedented scale. We serve Googlers, Google Cloud customers, and billions of Google users globally, driving Google's technological advancements.

We are the engine behind Google's remarkable innovations. Our work empowers the development of cutting-edge AI models, delivers immense computing power to worldwide services, and provides the foundational platforms for developers to build the future. Our diverse teams contribute to world-leading hyperscale computing, focusing on areas like TPUs, Vertex AI for Google Cloud, Global Networking, Data Center operations, and systems research.

Analyze the instruction set and architecture of Machine Learning (ML) Intellectual Property (IP) cores, leading discussions on new features compared to previous generations. Develop functional or performance models for these ML IPs, integrating functional models with the Cloud TPU System-on-Chip (SoC) model to establish a definitive architectural reference. Collaborate with pre-silicon verification and post-silicon validation teams to successfully deploy these models within their validation frameworks. Partner with compiler and software development teams to facilitate early development activities (left-shift).

- Study the instruction set and architecture of the Machine Learning (ML) IPs. - Drive discussions on delta features from the previous generation. - Develop functional or performance models for the ML IPs. - Integrate functional models with the Cloud TPU SoC model. - Deliver the single source of truth architectural reference. - Work with pre-silicon verification and post-silicon validation teams. - Deploy models into their validation flows. - Work with compiler and software teams. - Enable them to left-shift their development activity.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field is required, alongside equivalent practical experience. Alternatively, a PhD is considered. You should possess at least two years of experience in creating simulation models for hardware intellectual property (IP) or a PhD. A strong foundation in developing software systems using modern C++ is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specific focus on computer architecture. Experience in applying computer architecture principles to tackle complex, open-ended problems is highly valued. Familiarity with hardware and software co-design is beneficial. Knowledge of digital logic design at the Register Transfer Level (RTL) using Verilog is important, as is understanding processor or accelerator designs and the process of mapping Machine Learning (ML) models to hardware architectures.