Join a pioneering team crafting custom silicon that drives Google's consumer products and Google Cloud innovations. You will contribute to creating next-generation hardware experiences, ensuring superior performance, efficiency, and seamless integration.

The AI and Infrastructure team is at the forefront of technological advancement, providing AI and Infrastructure solutions at an unprecedented scale for Google customers, including internal teams, Google Cloud users, and billions of global users. Our work fuels Google's breakthroughs in AI, provides massive computing power for global services, and builds essential platforms for developers shaping the future.

- Analyze the instruction set and architecture of Machine Learning (ML) IPs, leading discussions on feature enhancements compared to previous generations. - Develop both functional and performance models for ML IPs. - Integrate functional models with the Cloud TPU SoC model to establish a unified architectural reference. - Collaborate with pre-silicon verification and post-silicon validation teams to implement these models within their validation workflows. - Partner with compiler and software teams to facilitate early development activities ('left-shift').

- Hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. - Possess at least 2 years of experience in developing simulation models for hardware IPs, or hold a PhD. - Demonstrated experience in developing software systems using modern C++. - Preferred candidates will have a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. - Experience applying computer architecture principles to address complex, open-ended challenges. - Familiarity with hardware and software co-design principles. - Knowledge of digital logic design at the Register Transfer Level (RTL) using Verilog is essential. - Understanding of processor design, accelerator designs, and mapping ML models to hardware architectures.