Join a pioneering team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be instrumental in shaping the next generation of hardware experiences, contributing to innovations that reach millions globally. Your expertise will be key in delivering unparalleled performance, efficiency, and seamless integration.

Our mission at Google is to make information universally accessible and useful. We achieve this by integrating Google's expertise in AI, software, and hardware to create profoundly helpful experiences. Our efforts focus on researching, designing, and developing cutting-edge technologies and hardware to advance computing power, speed, and seamlessness, ultimately aiming to improve lives through technology.

You will lead the design, implementation, and management of Integrated Circuit (IC) product bring-up, verification, and characterization programs for new product introductions (NPI). This includes developing ATE test programs, load boards, and probe cards using ATE platforms such as UFLEX or 93K.

Key responsibilities involve driving test development, validation, and characterization for high-speed interfaces, including DDR memory and High-Speed I/O (HSIO) IPs, to ensure production screen enablement and maintain low Defective Parts Per Million (DPPM). You will also collaborate with vendors and internal teams to engineer high-volume ATE manufacturing solutions optimized for advanced packaging.

Furthermore, you will execute product and DPPM correlation between ATE and system-level environments for new products, enhancing test coverage and resolving failure modes through rigorous troubleshooting on ATE and SLT systems. Directing production sustaining activities, such as program upgrades, yield optimization, test time reduction, lot disposition, and RMA analysis, will also be a core part of this role.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, or equivalent practical experience is required, coupled with 8 years of experience in the Semiconductor Domain. Essential experience includes ATE test program development, hardware architecture, and post-silicon bring-up for complex Digital/Mixed-Signal SoCs. Proficiency in ASIC/SoC test development, bring-up, or debug is also a must.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field. Experience with ATE platforms like Teradyne UltraFlex SOC and Advantest 93K, along with knowledge of high-speed interfaces such as DDR, PCIe, and SERDES, is highly desirable. A strong background in semiconductor processing, VLSI product/test engineering, and SLT expertise using the Advantest platform would be a significant asset.