Join a pioneering team at Google Cloud, crafting custom silicon solutions that drive the future of our direct-to-consumer products. You'll play a vital role in innovating products used by millions globally, shaping next-generation hardware for unparalleled performance, efficiency, and integration.

Our Technical Infrastructure team builds the robust architecture behind every Google product. From data center development to next-generation platform engineering, we make Google's vast product portfolio a reality. We thrive on optimizing systems, ensuring our networks deliver the fastest and most reliable user experiences.

Lead the SoC/SS integration team, guiding the development of complex IPs and Subsystems within our Bengaluru design organization.

Take ownership of microarchitecture and implementation for IPs and subsystems.

Collaborate closely with Architecture, Firmware, and Software teams to achieve feature closure and finalize microarchitecture specifications.

Drive design methodologies, library usage, debugging, and code reviews in alignment with other IP Design Verification (DV) and physical design teams.

Identify and champion Power, Performance, and Area (PPA) improvements for your designated domains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

Possess at least 10 years of experience in ASIC development, utilizing Verilog/SystemVerilog, VHDL, or Chisel.

Demonstrate 5 years of experience in the micro-architecture and design of SoCs and subsystems.

Bring 4 years of experience in people management and employee development.

Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) is essential.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Familiarity with SoC designs and integration flows, along with knowledge of arithmetic units, bus architectures, processor design, accelerators, memory hierarchies, and high-performance/low-power design techniques, is highly advantageous.