Join a pioneering team developing cutting-edge custom silicon solutions that will define the future of Google's direct-to-consumer products. You will be instrumental in creating innovative hardware that resonates with millions globally, shaping next-generation computing experiences with exceptional performance, efficiency, and integration.

As a High-Speed Input/Output (HSIO) Physical Layer (PHY) Verification Lead, you will spearhead the development of our custom silicon, focusing on high-speed interfaces. Your role will ensure seamless integration and optimal performance at both sub-system and SoC levels. Close collaboration with global, cross-functional teams, including design, architecture, and post-silicon validation, will be key to guiding our hardware from inception through successful silicon bring-up.

Lead the integration verification for HSIO PHY at the sub-system and SoC levels. Drive the creation of SoC-level test cases, effectively porting HSIO PHY IP-level test cases to the SoC environment. Oversee and execute regressions across RTL, Gate-Level Simulations (GLS), and Timing simulations. Conduct HSIO PHY virtual tester (VT) simulations in RTL, GLS, and Timing environments. Own testbench bring-up, including the integration of third-party Verification IP (VIP). Generate EVCD and bench collaterals for test cases to aid downstream validation. Perform in-depth waveform debugging and resolve complex digital design and verification challenges.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience is required.

Minimum of 8 years of experience in verification methodologies, including C, SystemVerilog, and constrained-random verification using OVM/UVM.

Proficiency in high-speed protocols such as USB2/USB3, PCIe, UFS, and MIPI, along with experience in loopback test concepts.

Demonstrated experience with HSIO PHY Controllers and porting PHY+ controller test cases.

Preferred qualifications include a Master's degree in a relevant technical field. Strong understanding of SoC-level interfaces and HSIO PHY register configurability is advantageous. Experience leading verification modules or mentoring junior engineers in complex SoC environments is beneficial. Familiarity with scripting languages like Python, Perl, SKILL, or Tcl for automating verification flows is a plus. A proven track record of successfully guiding complex mixed-signal/HSIO IPs through pre-silicon verification to post-silicon validation is highly valued.