Join a pioneering team developing custom silicon solutions to power Google's consumer products and shape the future of hardware. Your expertise will be instrumental in delivering next-generation hardware with exceptional performance, efficiency, and integration.

As the SoC Analog Integration Lead, you will spearhead the strategy, selection, and integration of high-speed analog and mixed-signal IPs, including PCIe, SerDes, DDR, and HBM PHYs, into complex SoCs. This role involves close collaboration with external and internal IP providers, SoC architects, package/board engineering, physical design, and post-silicon validation teams. You will manage the entire lifecycle of analog IP integration, ensuring adherence to stringent requirements for performance, power, thermal, area, floorplan, signal integrity, and system-level interfaces from architecture through production.

The AI and Infrastructure team is dedicated to pushing the boundaries of what's possible. We empower Google customers with advanced capabilities and insights through AI and Infrastructure at an unprecedented scale, efficiency, and reliability. Our impact spans across Googlers, Google Cloud customers, and billions of users globally. We are the engine behind Google's groundbreaking innovations, driving the development of cutting-edge AI models, delivering immense computing power to global services, and providing foundational platforms for developers building the future. Our work encompasses software and hardware, shaping world-leading hyperscale computing with teams focused on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead the comprehensive evaluation and selection process for third-party analog/mixed-signal IPs, such as PCIe, SerDes, and HBM PHYs. Establish detailed technical Service Level Agreements (SLAs), functional specifications, and delivery timelines.

Serve as the primary technical liaison with IP vendors, managing technical reviews, tracking bugs, evaluating silicon errata, and overseeing waiver processes.

Collaborate closely with floorplan and physical design teams to define precise integration requirements, ensuring alignment on critical aspects like placement, power delivery, clocking strategies, and functional interfaces.

Partner with packaging, PCB, and SI teams to optimize high-speed trace routing and power delivery networks, actively driving the die-package co-design process.

Oversee crucial AMS simulations and netlist checks, while also leading post-silicon bring-up, lab characterization (including BER and jitter analysis), and validation to facilitate successful product ramp-up.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a comparable field is required. Alternatively, equivalent practical experience will be considered.

Possess a minimum of 10 years of experience in analog and mixed-signal IPs, with expertise in areas like PCIe, UCIe, Serdes, HBM, or DDR PHYs, particularly within advanced technology nodes.

Demonstrate a strong track record of negotiating technical specifications and effectively managing technical deliverables with IP vendors.

A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture, is preferred.

Experience encompassing architectural requirements, physical design, packaging and board constraints, and system considerations for high-speed IO and memory PHYs is advantageous.

Experience in planning or utilizing DFT hooks and on-chip telemetry to support silicon health monitoring and bring-up workflows is a plus.

Proven ability to successfully integrate complex IOs and mixed-signal IPs into SoCs, along with experience in post-silicon validation to achieve production quality.

Demonstrated expertise in managing end-to-end technical evaluations, performance assessments, and QA sign-offs with third-party analog IP vendors.