Join a pioneering team developing custom silicon solutions that will power the future of Google's direct-to-consumer products. Your expertise will be instrumental in shaping next-generation hardware, driving unparalleled performance, efficiency, and integration.

As the SoC Analog Integration Lead, you will spearhead the strategy, selection, architectural, and physical integration of high-speed analog and mixed-signal IPs—including PCIe, SerDes, DDR, and HBM PHYs—into complex, high-performance SoCs.

This role involves close collaboration with external and internal IP providers, SoC architects, package/board engineering teams, physical design, timing, floorplan, and post-silicon validation teams. You will manage the entire lifecycle of analog IP integration, ensuring adherence to stringent performance, power, thermal, area, floorplan, signal integrity, and system-level interface requirements from early architecture through to volume production.

Lead the evaluation and selection of third-party analog/mixed-signal IPs (e.g., PCIe, SerDes, HBM PHY), defining detailed technical SLAs, functional specifications, and delivery schedules.

Act as the primary technical liaison with IP vendors, managing technical reviews, bug tracking, silicon errata evaluations, and waiver processes.

Collaborate with floorplan and physical design teams to establish integration requirements, ensuring alignment on placement, power delivery, clocking, and functional interfaces.

Partner with packaging, PCB, and SI teams to optimize high-speed trace and power delivery, driving the die-package co-design process.

Oversee AMS simulations and netlist checks, while leading post-silicon bring-up, lab characterization (BER, jitter), and validation to support the product ramp.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Minimum of 10 years of experience in analog and mixed-signal IPs such as PCIe, UCIe, Serdes, HBM, or DDR PHYs within advanced technology nodes.

Demonstrated experience in negotiating technical specifications and managing technical deliverables with IP vendors.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience across architectural requirements, physical design, packaging and board constraints, and system considerations for high-speed IO and memory PHYs is highly valued. Familiarity with planning or utilizing DFT hooks and on-chip telemetry for silicon health monitoring and bring-up workflows is beneficial. A proven track record of successfully integrating complex Ios and mixed-signal IPs into SoCs, along with experience in post-Si efforts to achieve production quality, is essential. Proven expertise in managing end-to-end technical evaluations, performance assessment, and QA sign-offs with third-party analog IP vendors is also a key asset.