Join a pioneering team at Google Cloud, dedicated to developing custom silicon solutions that will power the future of Google's direct-to-consumer products. You will be instrumental in shaping the next generation of hardware, driving innovation for products used by millions globally. Your expertise will be key in delivering unparalleled performance, efficiency, and integration for groundbreaking hardware experiences.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We empower Google customers with advanced capabilities and insights through AI and Infrastructure delivered at an unprecedented scale, efficiency, and reliability. Our reach extends to Googlers, Google Cloud customers, and billions of users worldwide. We are the engine behind Google's most significant innovations, supporting cutting-edge AI models, providing immense computing power for global services, and building the foundational platforms for future developer endeavors. Our work spans software and hardware, influencing the future of hyperscale computing, including TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

As the SoC Analog Integration Lead, you will drive the strategy, selection, architectural and physical integration, and silicon execution of high-speed analog and mixed-signal IPs. This includes critical components like PCIe, SerDes, DDR, and HBM PHYs, integrating them into complex, high-performance SoCs.

Your role involves close collaboration with external and internal IP providers, SoC architects, package/board engineering, physical design, timing, floorplan teams, and post-silicon validation teams. You will own the entire lifecycle of analog IP integration, ensuring all performance, power, thermal, area, floorplan, signal integrity, and system-level interface requirements are rigorously met from initial architecture through to high-volume production.

Key responsibilities include: - Leading the evaluation and selection of third-party analog/mixed-signal IPs, establishing detailed technical SLAs, functional specifications, and delivery schedules. - Serving as the primary technical liaison with IP vendors, managing technical reviews, bug tracking, silicon errata evaluations, and waiver processes. - Collaborating with floorplan and physical design teams to define integration requirements, ensuring alignment on placement, power delivery, clocking, and functional interfaces. - Partnering with packaging, PCB, and SI teams to optimize high-speed trace and power delivery, guiding the die-package co-design process. - Overseeing AMS simulations and netlist checks, and leading post-silicon bring-up, lab characterization (BER, jitter), and validation to support product ramp.

We are seeking a candidate with a minimum of 10 years of experience in analog and mixed-signal IPs such as PCIe, UCIe, Serdes, HBM, or DDR PHYs, particularly within advanced technology nodes. A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required.

Demonstrated experience in negotiating technical specifications and managing technical deliverables with IP vendors is essential. A strong understanding of architectural requirements, physical design, packaging, board constraints, and system considerations for high-speed IO and memory PHYs is highly valued.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience planning or utilizing DFT hooks and on-chip telemetry for silicon health monitoring and bring-up workflows is beneficial. A proven track record of successfully integrating complex Ios and mixed-signal IPs into SoCs, along with experience in taking SoCs to production quality post-Si, is a significant advantage. Candidates should also possess proven expertise in managing end-to-end technical evaluations, performance assessments, and QA sign-offs with third-party analog IP vendors.