Join a leading tech company and shape the future of AI/ML hardware acceleration. This role offers the opportunity to work on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Be part of a team that pushes boundaries, developing custom silicon solutions for Google's TPU.

Leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will solve technical challenges with innovative and practical logic solutions, considering complexity, performance, power, and area.

Collaborate with architecture, verification, power and performance, and physical design teams to deliver high-quality designs for next-generation data center accelerators. This position is part of the Technical Infrastructure team, responsible for the architecture that keeps Google's services running smoothly.

Take ownership of the microarchitecture and implementation of complex IPs and subsystems.

Ensure the RTL implementation and quality of one or more modules.

Contribute to design methodology, libraries, debug, and code reviews in collaboration with other IP Design Verification (DV) and physical design teams.

Identify and drive improvements in Power, Performance, and Area (PPA) for owned modules.

Participate in synthesis, timing/power closure, and FPGA/silicon bring-up processes.

Requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

Must have 8 years of experience in Application-Specific Integrated Circuit/System on a Chip (ASIC/SoC) development using Verilog/SystemVerilog.

Experience in micro-architecture and design of IPs and subsystems is essential.

Proven experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) is required.