Join Google Cloud as a Senior RTL Engineer and shape the future of AI/ML hardware acceleration. You will be instrumental in driving cutting-edge TPU technology that powers Google's most demanding AI/ML applications.

This role offers a unique opportunity to develop custom silicon solutions for Google's TPU. You'll contribute to innovations behind widely used products and apply your design and verification expertise to complex digital designs, with a particular focus on TPU architecture and its integration within AI/ML systems.

Be part of a dynamic team focused on developing SoCs for accelerating Machine Learning computation in data centers. You will tackle technical challenges with innovative, practical logic solutions and meticulously evaluate design options considering complexity, performance, power, and area.

Our Technical Infrastructure team builds and maintains the essential architecture that supports Google's online services. From data center development to next-generation platform engineering, we enable Google's entire product portfolio. We pride ourselves on being engineers' engineers, constantly optimizing and rebuilding systems to ensure optimal network performance and user experience.

Take the lead in defining the microarchitecture and implementing complex Intellectual Property (IP) blocks and subsystems.

Assume responsibility for RTL implementation and conduct thorough quality checks for assigned modules.

Collaborate with cross-functional teams, including Design Verification (DV) and physical design, to advance design methodologies, libraries, debugging processes, and code reviews.

Proactively identify and spearhead initiatives to enhance Power, Performance, and Area (PPA) for owned modules.

Engage in critical stages such as synthesis, timing/power closure, and FPGA/silicon bring-up.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field is required, or equivalent practical experience.

Minimum of 8 years of experience in Application-Specific Integrated Circuit/System on a Chip (ASIC/SoC) development, utilizing Verilog/SystemVerilog.

Demonstrated experience in micro-architecture and the design of IPs and subsystems.

Proven experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications include experience with programming languages like Python, C/C++, or Perl, and familiarity with SoC design and integration flows. Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC, memory hierarchies, and high-performance/low-power design techniques is highly advantageous.