Join a pioneering team shaping the future of AI/ML hardware acceleration by driving cutting-edge Tensor Processing Unit (TPU) technology. This role offers the chance to develop custom silicon solutions that power Google's most demanding AI/ML applications and contribute to innovations used by millions globally. You'll leverage your expertise in design and verification to ensure the integrity of complex digital designs, focusing on TPU architecture and its seamless integration within AI/ML-driven systems.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We empower Google customers with unparalleled AI and Infrastructure capabilities, ensuring scale, efficiency, and reliability. Our innovations fuel Google's AI models, provide immense computing power for global services, and create essential platforms for developers.

This is an opportunity to be part of a team that builds the future of world-leading hyperscale computing, contributing to TPUs, Vertex AI for Google Cloud, and more.

Architect, model, analyze, and design next-generation TPUs in close collaboration with hardware and software architects. Drive product definition and implementation, balancing performance, power, features, schedule, and cost. Characterize and benchmark ML workloads, proposing optimizations for future TPUs. Develop architecture specifications for AI/ML roadmaps, creating power/performance models, RTL designs, and evaluating their effectiveness.

Foster effective hardware/software co-design through partnerships with design, software, compiler, and research teams. Implement and adopt advanced AI/ML capabilities and drive efficient verification strategies. Utilize AI techniques to optimize physical design convergence, including timing, floor planning, power grids, and clock trees. Investigate and optimize DFT, post-silicon testing, and debug strategies for silicon bring-up and qualification.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, or a related technical field is required, alongside equivalent practical experience. Proficiency in programming languages such as C++, Python, and Verilog is essential. Experience with accelerator architectures and data center workloads is a must.

Preferred qualifications include 2 years of silicon engineering experience post PhD. Familiarity with performance modeling tools and knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies are advantageous. Experience with high-performance and low-power design techniques is also beneficial.