Shape the future of AI/ML hardware acceleration by driving Tensor Processing Unit (TPU) technology that powers Google's most demanding AI/ML applications. You will be instrumental in developing custom silicon solutions for Google's TPUs, contributing to innovations that impact millions worldwide.

Leverage your expertise in design and verification to ensure the accuracy of complex digital designs, with a special focus on TPU architecture and its seamless integration within AI/ML systems. Collaborate with hardware and software architects and designers to define, model, and design next-generation TPUs.

Responsibilities include balancing performance, power, features, schedule, and cost through dynamic, multi-faceted contributions to product definition, design, and implementation. The AI and Infrastructure team is at the forefront of delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity, empowering Google customers with breakthrough capabilities and insights.

Revolutionize Machine Learning (ML) workload characterization and benchmarking, proposing capabilities and optimizations for next-generation TPUs. Develop architecture specifications that align with current and future AI/ML roadmap requirements. Create architectural and microarchitectural power/performance models, RTL designs, and conduct quantitative performance and power analysis.

Collaborate with hardware design, software, compiler, ML model, and research teams for effective hardware/software co-design and high-performance interface creation. Develop and implement advanced AI/ML capabilities and drive efficient design verification strategies.

Utilize AI techniques for faster and optimal physical design convergence, including timing, floor planning, power grid, and clock tree design. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies for silicon bring-up and qualification.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience is required.

Demonstrated experience in programming languages such as C++, Python, and Verilog. Proficiency with Synopsys and Cadence tools is essential.

Experience with accelerator architectures and data center workloads is a key requirement. Additionally, 2 years of silicon engineering experience post-PhD and familiarity with performance modeling tools are preferred qualifications. Knowledge of arithmetic units, bus architectures, accelerators, memory hierarchies, and high-performance/low-power design techniques is beneficial.