Shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer. Drive Tensor Processing Unit (TPU) technology that powers Google's most demanding AI/ML applications. Collaborate with hardware and software architects to define and design next-generation TPUs. You will balance performance, power, features, schedule, and cost.

The AI and Infrastructure team redefines possibilities, empowering customers with breakthrough capabilities and insights through large-scale AI and Infrastructure delivery. We enable Google's innovations, provide unparalleled computing power, and offer platforms for developers. Our teams are shaping world-leading hyperscale computing, including TPUs, Vertex AI, Global Networking, and Data Center operations.

Revolutionize Machine Learning (ML) workload characterization and benchmarking, proposing optimizations for next-generation TPUs. Develop architecture specifications for the AI/ML roadmap. Create architectural and microarchitectural power/performance models, microarchitecture, and RTL designs. Evaluate quantitative and qualitative performance and power. Partner with hardware design, software, compiler, ML model, and research teams for effective hardware/software co-design. Develop and adopt advanced AI/ML capabilities and drive efficient design verification strategies.

Utilize AI techniques for faster physical design convergence, including timing, floor planning, and power grid design. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to silicon bring-up and qualification.

A PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience is required. Expertise in programming languages like C++, Python, and Verilog is essential. Proficiency with Synopsys and Cadence tools is necessary.

Demonstrated experience with accelerator architectures and data center workloads is critical. Preferred qualifications include 2 years of silicon engineering experience post-PhD, familiarity with performance modeling tools, and knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Experience with high-performance and low-power design techniques is also highly valued.