Join Google's AI and Infrastructure team and help shape the future of AI/ML hardware acceleration. You will drive Tensor Processing Unit (TPU) technology that powers Google's most demanding AI/ML applications. This role offers the opportunity to develop custom silicon solutions and contribute to innovation behind products used by millions worldwide. You'll leverage your expertise in design and verification, focusing on TPU architecture and its integration within AI/ML-driven systems.

As a Silicon Architect/Design Engineer, you will collaborate with hardware and software architects to define and design next-generation TPUs. Your responsibilities will encompass product definition, design, and implementation, balancing performance, power, features, schedule, and cost. This team is at the forefront of redefining AI and Infrastructure, empowering Google customers with breakthrough capabilities at unparalleled scale, efficiency, and reliability.

We are developing the core technologies behind Google's groundbreaking innovations, including our TPUs, Vertex AI for Google Cloud, and global networking infrastructure. Our work enables the development of advanced AI models and provides the computing power essential for global services and developer platforms.

Revolutionize Machine Learning (ML) workload characterization and benchmarking, proposing optimizations for future TPUs. Develop architecture specifications to meet evolving AI/ML roadmap requirements. Create architectural and microarchitectural power/performance models, RTL designs, and conduct performance/power analysis. Collaborate with hardware, software, compiler, and ML model teams for effective hardware/software co-design and high-performance interface development. Adopt advanced AI/ML capabilities and drive efficient design verification strategies and implementations. Utilize AI techniques for faster and optimal physical design convergence (timing, floor planning, power grid, clock tree). Investigate, validate, and optimize DFT, post-silicon test, and debug strategies for silicon bring-up and qualification.

Possess a PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience. Proficient in programming languages such as C++, Python, and Verilog. Experience with Synopsys and Cadence tools is essential. Familiarity with accelerator architectures and data center workloads is required.

Preferred qualifications include: 2 years of silicon engineering experience post-PhD. Experience with performance modeling tools. Knowledge of arithmetic units, bus architectures, accelerators, or memory hierarchies. Understanding of high-performance and low-power design techniques.