Join a pioneering team developing cutting-edge custom silicon solutions that drive Google's consumer products. You will play a crucial role in shaping the future of hardware, contributing to innovations that reach millions worldwide. Your expertise will define the next generation of hardware, delivering exceptional performance, efficiency, and seamless integration.

This role involves developing SoCs for accelerating machine learning computations in data centers. You will collaborate closely with architecture, verification, power, performance, and physical design teams to deliver high-quality designs. You will tackle complex technical challenges with innovative micro-architectural and logical solutions, evaluating design trade-offs in terms of complexity, performance, power, and area.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced AI capabilities and insights at an unprecedented scale. We deliver AI and Infrastructure solutions with exceptional efficiency, reliability, and speed. Our impact extends to Googlers, Google Cloud clients, and billions of users globally.

We are the driving force behind Google's transformative innovations, enabling the development of AI models, providing immense computing power for global services, and building the foundational platforms for future developer endeavors. Our teams, spanning software and hardware, are shaping the future of world-class hyperscale computing, with significant contributions to TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead and mentor a team, establishing clear individual and team priorities aligned with organizational objectives. Conduct regular performance and development discussions, offering constructive feedback and coaching.

Assume full ownership of Static Timing Analysis (STA) for physical design partitions and the top-level design.

Drive the resolution of timing and power consumption issues within the design.

Contribute to the enhancement of design methodologies, libraries, and participate in code reviews.

Establish and define the physical design STA constraint rule sets for the physical design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience is required.

Possess 10 years of advanced design experience, encompassing clock/voltage domain crossing, Design for Testing (DFT), and low-power design methodologies.

Bring 6 years of experience in people management, with a proven track record of developing and mentoring employees.

Demonstrated experience in achieving Static Timing Analysis (STA) convergence for blocks, subsystems (SS), or entire SoCs.

Experience with System on a Chip (SoC) design cycles is essential.

Expertise in high-performance, high-frequency, and low-power design domains is a must.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Familiarity with scripting languages like Perl, Python, or Tcl is beneficial. Experience in Very-Large-Scale Integration (VLSI) design for SoCs or multiple SoC ASIC design cycles is advantageous. Proficiency in coding constraints and scripting with TCL is also preferred.