Join a forward-thinking team crafting custom silicon solutions that power Google's innovative direct-to-consumer products. You will be instrumental in shaping the next generation of hardware, delivering exceptional performance, efficiency, and seamless integration for products enjoyed by millions globally.

This role involves developing System on Chips (SoCs) essential for accelerating machine learning computations within data centers. You will collaborate closely with architecture, verification, power, performance, and physical design teams to deliver high-quality designs for next-generation data center accelerators. Your contributions will involve solving complex technical challenges through innovative micro-architectures and practical logic solutions, while thoroughly evaluating design trade-offs regarding complexity, performance, power, and area.

Lead and mentor a team, establishing clear priorities aligned with organizational objectives. Conduct regular performance and development discussions, providing constructive feedback and coaching.

Take full ownership of Static Timing Analysis (STA) for physical design partitions and the overall system. Drive the successful closure of timing and power consumption for the design.

Contribute to advancing design methodologies, libraries, and participating in code reviews. Define comprehensive physical design STA constraint rule sets for the engineering team.

Requires a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with equivalent practical experience. Possess a minimum of 10 years of advanced design experience, including expertise in clock/voltage domain crossing, Design for Testing (DFT), and low power designs.

Minimum of 6 years in people management, with a proven track record in employee development. Demonstrable experience in Static Timing Analysis (STA) convergence for blocks, subsystems (SS), or entire SoCs. Familiarity with System on Chip (SoC) design cycles and experience in high-performance, high-frequency, and low-power design environments.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience with scripting languages such as Perl, Python, or Tcl is advantageous. Familiarity with Very-Large-Scale Integration (VLSI) design in SoC contexts or experience with multiple SoC ASIC design cycles is also preferred. Proficiency in coding constraints and scripting using TCL is a plus.