Join a pioneering team focused on developing custom silicon solutions that power Google's cutting-edge direct-to-consumer products. You will play a key role in shaping the future of hardware, contributing to innovations that enhance user experiences with unparalleled performance and efficiency.

This role involves working on System on a Chip (SoC) development for accelerating machine learning computations within data centers. You will collaborate closely with architecture, verification, power, and performance teams to deliver high-quality designs. Your contributions will involve solving complex technical challenges through innovative micro-architecture and logic solutions, while meticulously evaluating design trade-offs concerning complexity, performance, power, and area.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced AI capabilities and insights. We deliver AI and Infrastructure solutions at an unprecedented scale, efficiency, and reliability. Our work supports Googlers, Google Cloud customers, and billions of users globally.

We are the engine behind Google's transformative innovations, driving the development of AI models, providing immense computing power for global services, and building the foundational platforms for future development. Our teams are instrumental in shaping world-leading hyperscale computing, with significant efforts dedicated to TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead and mentor a team of individuals, establishing clear team and individual priorities aligned with organizational objectives. Conduct regular performance and development discussions, providing constructive feedback and coaching.

Assume full ownership of Static Timing Analysis (STA) for designated physical design partitions and the top-level design. Drive the resolution of timing and power consumption issues to ensure optimal design performance.

Contribute to the advancement of design methodologies, libraries, and conduct code reviews to maintain high standards. Define and establish robust physical design STA constraint rule sets for the physical design engineering team.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience is required. You should possess 10 years of experience in advanced design areas, including clock/voltage domain crossing, Design for Testing (DFT), and low-power designs.

Significant experience of 6 years in people management and employee development is essential. Experience with Static Timing Analysis (STA) convergence on blocks, Subsystems (SS), or SoCs is crucial. Familiarity with System on a Chip (SoC) cycles and expertise in high-performance, high-frequency, and low-power designs are expected.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience with scripting languages like Perl, Python, or Tcl is beneficial. Proficiency in Very-Large-Scale Integration (VLSI) design within an SoC context, or experience across multiple SoC ASIC design cycles, is advantageous. Experience in coding constraints and scripting using TCL is also highly desirable.