Join a forward-thinking team dedicated to creating cutting-edge custom silicon solutions that power Google's direct-to-consumer products. Your contributions will be instrumental in driving innovation for products used by millions globally. This role is key to shaping the next generation of hardware, ensuring exceptional performance, efficiency, and seamless integration.

This position involves developing SoCs crucial for accelerating machine learning computations within data centers. You will collaborate closely with architecture, verification, power, performance, and physical design teams to deliver high-quality designs for future data center accelerators. You'll tackle complex technical challenges with innovative micro-architectural and practical logic solutions, evaluating design trade-offs concerning complexity, performance, power, and area.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We empower Google customers with advanced capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our user base spans Googlers, Google Cloud customers, and billions of users worldwide.

We are the engine behind Google's most significant innovations, enabling the development of AI models, providing immense computing power for global services, and offering the foundational platforms for developers to build the future. Our teams, encompassing both software and hardware, are instrumental in shaping the trajectory of world-leading hyperscale computing. Key areas of focus include the development of TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Lead and mentor a team, establishing clear individual and team priorities that align with organizational objectives. Conduct regular performance and development discussions, providing constructive feedback and coaching.

Assume responsibility for the Static Timing Analysis (STA) of physical design partitions and the overall chip. Drive the resolution of timing and power consumption issues within the design.

Contribute to the advancement of design methodologies, library development, and code review processes. Define and implement the physical design STA constraint rule sets for the engineering team.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is required. A minimum of 10 years of experience in advanced design, covering aspects like clock/voltage domain crossing, Design for Testing (DFT), and low-power designs, is essential. Additionally, 6 years of experience in people management and employee development is necessary.

Proven experience with Static Timing Analysis (STA) convergence at block, subsystem (SS), or SoC levels. Familiarity with System on a Chip (SoC) cycles and experience in high-performance, high-frequency, and low-power design environments are also key.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with scripting languages like Perl, Python, or Tcl is advantageous. Further desirable skills include Very-Large-Scale Integration (VLSI) experience in SoC design or multiple cycles of ASIC design, along with proficiency in coding constraints and scripting using TCL.