Join a pioneering team at Google Cloud, shaping the future of custom silicon solutions that power our direct-to-consumer products. You will be instrumental in developing SoCs designed to accelerate machine learning computation within data centers, collaborating with experts across architecture, verification, and power/performance teams.

Your role will involve delivering high-quality designs for next-generation data center accelerators. You'll tackle complex technical challenges by devising innovative micro-architectural and logic solutions, carefully evaluating design trade-offs related to complexity, performance, power, and area.

The AI and Infrastructure team is at the forefront of redefining technological possibilities. We equip Google customers with cutting-edge AI capabilities and insights, delivering AI and Infrastructure solutions at unprecedented scale, efficiency, and reliability. Our impact reaches Googlers, Google Cloud customers, and billions of users globally, driving Google's groundbreaking innovations from AI models to hyperscale computing platforms.

As a Silicon Physical Design STA Lead, you will guide and mentor a team, establishing clear priorities aligned with organizational objectives. You will conduct regular performance and development discussions, offering constructive feedback and coaching.

Take direct ownership of the Static Timing Analysis (STA) for critical physical design partitions and the overall top level. Your focus will be on driving the convergence of timing and power consumption for the design.

Contribute significantly to the refinement of design methodologies, libraries, and code review processes. You will also be responsible for defining the physical design STA constraint rule sets for the physical design engineers.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline is required, or equivalent practical experience.

We are looking for 10 years of experience in advanced design, including expertise in clock/voltage domain crossing, Design for Testing (DFT), and low-power design techniques. Additionally, 6 years of experience in people management and employee development is essential.

Demonstrated experience with Static Timing Analysis (STA) convergence on blocks, subsystems (SS), or SoCs is crucial. Familiarity with System on a Chip (SoC) cycles and a background in high-performance, high-frequency, and low-power designs are also required.