Join a pioneering team dedicated to developing advanced custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be instrumental in shaping innovative hardware experiences, delivering exceptional performance, efficiency, and seamless integration for products used by millions globally.

This role is crucial in advancing the next generation of hardware, contributing significantly to the cutting-edge technologies powering Google's ecosystem. Your contributions will directly influence the performance and capabilities of consumer-facing innovations.

As a Physical Design Engineer, you will focus on enhancing Design Power, Performance, and Area (PPA) through a variety of sophisticated techniques. You will leverage your expertise in physical design and machine learning to tackle complex technical challenges.

Key responsibilities include collaborating with RTL, DV, and DFT teams to optimize PPA and schedules, directly impacting logic design, floorplanning, place and route, clock and power planning, timing analysis, and PDN analysis. You will also collaborate with cross-functional teams across Alphabet, including design, CAD, and machine learning specialists.

You will take complete ownership from synthesis to GDS implementation for intricate physical partitions. This includes partnering with sign-off teams to ensure convergence on EM/IR, power, timing, and physical verification. You will also drive improvements in CAD methodologies for PPA benefits.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field is required, alongside equivalent practical experience. A minimum of 4 years of dedicated experience in physical design is essential.

Proven experience in high-performance synthesis, Place and Route (PnR), and sign-off optimizations is critical. This includes demonstrated expertise in sign-off convergence, covering Static Timing Analysis (STA), electrical checks, and physical verification.

Proficiency in programming with TCL/Python is necessary. A Master's degree or PhD in a relevant engineering or computer science field, with a focus on computer architecture, is preferred. Experience with constraints, synthesis, or Clock Tree Synthesis (CTS) is also a plus, as is experience applying Machine Learning (ML) to physical design or sign-off convergence.

Knowledge of Verilog/SystemVerilog and a foundational understanding of circuit design, device physics, and deep submicron technology are beneficial. In-person interviews are typically part of the hiring process for this position.