Join a pioneering team crafting custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be instrumental in developing innovative hardware experiences, enhancing performance, efficiency, and integration for next-generation products used by millions globally.

This role requires in-person interviews as part of the selection process. As a Physical Design Engineer, you will focus on optimizing design power, performance, and area (PPA) through advanced techniques. You will leverage your expertise in physical design and machine learning to tackle complex technical challenges, collaborating with RTL, DV, and DFT teams to enhance PPA and project timelines. Your contributions will directly influence logic design, floor planning, place and route, clock and power distribution, timing analysis, and PDN analysis.

You will work across Alphabet with design, CAD, and machine learning specialists. The Platforms and Devices team focuses on Google's diverse computing software platforms and first-party devices, integrating Google AI, software, and hardware. These teams drive innovation in user interaction with computing, making it faster and more seamless worldwide.

- Drive the end-to-end synthesis to GDS implementation for intricate physical partitions and subsystems. - Collaborate with sign-off teams, taking ownership of EM/IR, power, timing, and physical verification convergence. - Partner with RTL, DFT, and CAD teams to achieve Power/Performance/Area improvements in physical design. - Enhance and utilize CAD recipes for significant PPA benefits.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required.

This role necessitates a minimum of 4 years of experience in physical design. Key areas of expertise include high-performance synthesis, Place and Route (PnR), and sign-off optimizations. Proficiency in sign-off convergence is essential, encompassing Static Timing Analysis (STA), electrical checks, and physical verification.

Experience with programming languages such as TCL and Python is also a must. Preferred qualifications include a Master's degree or PhD in relevant engineering fields with a computer architecture focus. Experience with constraints, synthesis, Clock Tree Synthesis (CTS), and applying Machine Learning (ML) to physical design challenges, particularly STA/EMIR closure, is advantageous. A solid understanding of Verilog/SystemVerilog, circuit design, device physics, and deep submicron technology is beneficial.