Join Google Cloud's innovation team and contribute to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will play a key role in shaping next-generation hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally.

This position focuses on designing Application-Specific Integrated Circuits (ASICs) for accelerating machine learning computations within data centers. You will collaborate closely with various teams, including Architecture, Verification, Power and Performance, and Physical Design, to deliver high-quality designs for future accelerators. Your work will involve innovative micro-architecture solutions and evaluating critical design trade-offs.

The AI and Infrastructure team is at the forefront of redefining possibilities, enabling Google customers with advanced AI capabilities at an unprecedented scale. We empower groundbreaking innovations, from cutting-edge AI models to essential platforms for developers, impacting billions of users worldwide.

Lead a team of engineers in delivering complex IP and subsystem designs. Effectively communicate and collaborate with diverse, multi-site, and multi-disciplinary teams.

Define detailed micro-architecture (uArch) specifications and block-level design documents, encompassing interface protocols, block diagrams, transaction flows, and pipeline architectures.

Engage in RTL development, subsystem integration, and SoC integration. Conduct essential checks including Lint, CDC, FV, and UPF.

Participate actively in simulation debugging, synthesis, timing and power closure, and the silicon bring-up process. Contribute to test plan development and coverage analysis for both block and SOC-level verification.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience is required.

Possess at least 10 years of experience in ASIC/SoC development, with a strong command of Verilog and SystemVerilog.

Demonstrated experience in micro-architecture design and the development of IPs and Subsystems is essential.

Proven experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) is a must.

Preferred qualifications include a Master's or PhD in relevant fields with a computer architecture focus, experience with scripting languages like Python or Perl, and a deep understanding of SoC designs, integration flows, and high-performance/low-power design methodologies.