Join a pioneering team at Google Cloud, driving innovation in custom silicon solutions for cutting-edge direct-to-consumer products. You'll significantly impact the future of hardware experiences, delivering exceptional performance, efficiency, and seamless integration.

This role focuses on developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computations within data centers. Collaboration with Architecture, Verification, Power & Performance, and Physical Design teams is key to delivering high-quality designs for next-generation accelerators. You will tackle complex technical challenges through micro-architecture innovation and expertly balance design trade-offs between performance and power consumption.

- Lead engineering teams in the design organization to successfully deliver intricate IPs or subsystems. - Foster clear communication and effective collaboration across multi-disciplinary and multi-site teams. - Define precise micro-architecture (uArch) specifications and detailed block-level design documents. - These documents will encompass interface protocols, block diagrams, transaction flows, and pipeline intricacies. - Execute RTL development, manage subsystem and System on a Chip (SoC) integration. - Perform essential checks including Lint, CDC, FV, and UPF.

- A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, coupled with equivalent practical experience. - A minimum of 10 years of hands-on experience in ASIC/SoC development, utilizing Verilog/SystemVerilog. - Proven experience in micro-architecture and the design of IPs and Subsystems. - Demonstrated experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).