Join a pioneering team developing custom silicon solutions that will define the future of Google's direct-to-consumer products. This role offers the opportunity to innovate and shape next-generation hardware, delivering exceptional performance, efficiency, and integration for products used by millions globally.

Our AI and Infrastructure team is dedicated to pushing the boundaries of what's possible, empowering Google customers with cutting-edge AI and infrastructure at an unprecedented scale. We are the driving force behind Google's groundbreaking innovations, from AI models and computing power to essential platforms for developers.

Lead engineering teams in designing complex Intellectual Property (IP) blocks and subsystems, fostering collaboration across multi-disciplinary and multi-site teams.

Key responsibilities include defining detailed micro-architecture specifications, creating block-level design documents, and managing RTL development, subsystem, and SoC integration.

Perform essential checks like Lint, CDC, FV, and UPF. You will also be involved in simulation debugging, synthesis, timing and power closure, and silicon bring-up.

Contribute to test plan development and coverage analysis for both block and SoC-level verification efforts.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, is essential. Candidates should possess at least 10 years of experience in ASIC/SoC development utilizing Verilog/SystemVerilog.

Proven experience in micro-architecture and the design of IPs and Subsystems is required. This includes expertise in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications include a Master's or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture. Experience with scripting languages like Python or Perl, SoC design and integration flows, and knowledge of high-performance and low-power design techniques are highly advantageous.