Join Google Cloud's innovative team to design custom silicon powering Google's direct-to-consumer products. You will shape next-generation hardware, driving unparalleled performance and efficiency. This role is instrumental in developing Application-Specific Integrated Circuits (ASICs) for accelerating machine learning in data centers.

Collaborate across Architecture, Verification, Power/Performance, and Physical Design teams to deliver high-quality designs for cutting-edge accelerators. Solve complex technical challenges through micro-architecture innovation and optimize design trade-offs between performance and power consumption.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with AI and Infrastructure at an unprecedented scale. Our work enables breakthrough capabilities for Googlers, Google Cloud clients, and billions of Google users worldwide, driving the future of computing.

Lead engineering teams in the design of complex Intellectual Property (IP) blocks or subsystems.

Effectively communicate and collaborate with diverse, multi-disciplinary, and geographically distributed teams.

Define precise micro-architecture (uArch) specifications and detailed block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline architectures.

Execute RTL development, manage subsystem and System on a Chip (SoC) integration, and perform essential checks like Lint, CDC, Formal Verification (FV), and UPF.

Actively participate in simulation debugging, synthesis, timing and power closure, and the crucial silicon bring-up process.

Contribute to test plan development and coverage analysis at both block and SoC levels for verification.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field is required, or equivalent practical experience.

Possess at least 10 years of hands-on experience in ASIC/SoC development using Verilog/SystemVerilog.

Demonstrate significant experience in micro-architecture and the design of IPs and Subsystems.

Proven experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) methodologies.

Preferred qualifications include a Master's or PhD in relevant engineering or computer science fields, with a focus on computer architecture. Experience with scripting languages like Python or Perl, and knowledge of SoC designs, integration flows, arithmetic units, bus architectures, processor design, accelerators, memory hierarchies, high-performance, and low-power design techniques are highly advantageous.