Join a pioneering team shaping the future of AI/ML hardware acceleration at Google Cloud. You will have a unique opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology, powering Google's most demanding AI/ML applications. Be part of a team pushing boundaries to develop custom silicon solutions that power the next generation of Google's TPUs.

Contribute to innovations behind products used by millions worldwide. Leverage your design and verification expertise to ensure the integrity of complex digital designs, with a specialized focus on TPU architecture and its seamless integration within AI/ML-driven systems. This role is integral to the Technical Infrastructure team, which builds and maintains the core architecture supporting Google's vast product portfolio.

Lead the development of complex Intellectual Property (IP) blocks and subsystems within the Bangalore design organization. Take ownership of the microarchitecture and implementation of these critical components. Collaborate closely with Architecture, Firmware (FW), and Software (SW) teams to finalize features and define detailed microarchitecture specifications. Drive advancements in design methodologies, library utilization, debugging techniques, and code reviews in coordination with other IP Design Verification (DV) and physical design teams.

Champion efforts to identify and implement Power, Performance, and Area (PPA) optimizations for your designated domains. This role requires a proactive approach to innovation and a commitment to delivering high-quality silicon solutions.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field is required, alongside equivalent practical experience. Candidates must possess at least 10 years of comprehensive experience in Application-Specific Integrated Circuit (ASIC)/System on Chip (SoC) development, with a strong command of Verilog and SystemVerilog.

Demonstrated experience in microarchitecture, IP design, and subsystem implementation is essential. Proficiency in ASIC design verification, synthesis, timing analysis, power analysis, and Design for Testability (DFT) is also a key requirement. Preferred qualifications include experience with programming languages such as Python, C/C++, or Perl, and familiarity with SoC design and integration flows.