Join a forward-thinking team dedicated to crafting custom silicon solutions that power Google Cloud's cutting-edge direct-to-consumer products. Your contributions will be instrumental in shaping the next generation of hardware, delivering exceptional performance, efficiency, and seamless integration for innovations used by millions globally.

This role offers a unique chance to influence the future of AI/ML hardware acceleration, driving advanced TPU technology for Google's most demanding applications. You will leverage your expertise in design and verification to ensure the robust functionality of complex digital designs, with a special focus on TPU architecture and its integration within AI/ML systems.

The AI and Infrastructure team is at the forefront of innovation, providing Google customers with transformative capabilities and insights. We deliver AI and Infrastructure at an unmatched scale, efficiency, reliability, and speed. Our impact reaches Googlers, Google Cloud clients, and billions of users worldwide.

We are the engine behind Google's pioneering advancements. Our teams empower the development of state-of-the-art AI models, provide immense computing power for global services, and build the foundational platforms enabling developers to create the future. From software to hardware, we are shaping hyperscale computing worldwide, with key efforts in TPU development, Vertex AI for Google Cloud, Global Networking, Data Center operations, and systems research.

Lead the development of intricate IPs and subsystems alongside a talented engineering team. Take ownership of the micro-architecture and implementation of IPs and subsystems. Collaborate with architecture, firmware, and software teams to finalize features and develop detailed micro-architecture specifications. Champion design methodologies, libraries, debug processes, and code reviews in partnership with other IP Design Verification (DV) and physical design teams. Identify and drive enhancements in power, performance, and area for your assigned domains.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a comparable field is required, or equivalent practical experience.

A minimum of 10 years of experience in ASIC development, proficiency in Verilog/SystemVerilog and VHDL is essential.

Demonstrated experience in micro-architecture and the design of IPs and subsystems.

Experience encompassing ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) is necessary.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture.

Familiarity with scripting languages such as Python or Perl is advantageous.

Experience with SoC designs and integration flows is beneficial.

Knowledge of business architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies is a plus.

Understanding of high-performance and low-power design techniques is desirable.