Join a groundbreaking team crafting custom silicon solutions that power Google's innovative direct-to-consumer products. You will be instrumental in developing the next generation of hardware experiences, driving unparalleled performance, efficiency, and integration.

The Silicon team is responsible for the design and fabrication of high-performance custom silicon and accelerators, crucial for Google's advancements in machine learning, Google Cloud, and hardware infrastructure.

As an ASIC Design Verification Engineer, you will play a key role in verifying next-generation custom silicon accelerators and SoCs. This involves building sophisticated UVM test environments and collaborating closely with design, architecture, and emulation teams to ensure the delivery of production-quality silicon.

The Platforms and Devices team focuses on Google's diverse computing software platforms across various environments, including desktop, mobile, and applications. We also develop our first-party devices and services, integrating Google AI, software, and hardware to create seamless and faster user interactions. Our teams are dedicated to researching, designing, and developing new technologies that build innovative experiences for users worldwide.

Develop comprehensive test plans, detailing verification strategies, environments, components, stimulus, checks, and coverage, ensuring clear and accessible documentation.

Plan the verification of digital design blocks by thoroughly understanding design specifications and partnering with design engineers to identify critical verification scenarios.

Construct and enhance constrained-random verification environments utilizing SystemVerilog and UVM. You may also leverage SystemVerilog Assertions (SVA) and formal tools for formal verification.

Execute power-aware simulations and formal verification to validate power management features such as clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, to ensure power integrity.

Design and implement coverage-driven verification plans to guarantee exhaustive coverage of ASIC designs. Work collaboratively with design engineers to address coverage gaps and elevate design quality.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience is required.

One year of experience in creating or utilizing verification components and environments within the UVM methodology at the IP or Subsystem level is essential.

Demonstrated experience in developing and maintaining design verification (DV) testbenches, test cases, and test environments.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on computer architecture.

Experience with image processing, computer vision, or machine learning IPs is advantageous.

Familiarity with AMBA (APB/AXI/ACE) or other standard protocols is beneficial.

Knowledge of CPU, GPU, or other computer architectures is a plus.