Join a pioneering team developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will drive innovation in hardware experiences, delivering exceptional performance and efficiency. The Silicon team focuses on high-performance custom silicon and accelerators that power Google's machine learning, cloud, and infrastructure.

As an ASIC Design Verification Engineer, you will validate cutting-edge custom silicon accelerators and SoCs. This involves building advanced UVM test environments and collaborating with design and architecture teams to ensure production-quality silicon.

The Platforms and Devices team works across Google's computing software platforms and first-party devices. We research and develop new technologies to enhance user interaction with computing, creating seamless and innovative experiences globally.

Develop comprehensive test plans, including verification strategy, environment setup, component integration, stimulus generation, checks, and coverage metrics. Ensure all documentation is clear and user-friendly.

Strategize and plan the verification of digital design blocks by thoroughly understanding design specifications. Collaborate closely with design engineers to pinpoint crucial verification scenarios.

Construct and refine constrained-random verification environments utilizing SystemVerilog and UVM. Optionally leverage SystemVerilog Assertions (SVA) and formal tools for advanced verification techniques.

Execute power-aware simulations and formal verification to validate power management functionalities such as clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, to ensure power integrity.

Design and implement coverage-driven verification plans to guarantee thorough coverage of ASIC designs. Work with design engineers to address coverage gaps and elevate overall design quality.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience is required.

Possess at least one year of hands-on experience in creating and utilizing verification components and environments within the UVM methodology at the IP or Subsystem level.

Demonstrated experience in developing and maintaining robust design verification (DV) testbenches, test cases, and comprehensive test environments is essential.