Join a pioneering team dedicated to crafting custom silicon solutions that drive the future of Google's direct-to-consumer products and AI/ML hardware acceleration. You will play a crucial role in advancing cutting-edge TPU technology powering Google's most demanding applications. Your expertise will help shape next-generation hardware experiences, delivering exceptional performance, efficiency, and integration for products used by millions globally.

The AI and Infrastructure team is at the forefront of innovation, providing unparalleled AI and Infrastructure capabilities at scale. We empower Google users, Google Cloud customers, and billions worldwide with breakthrough advancements.

Our team is the engine behind Google's transformative innovations. We fuel the development of advanced AI models, deliver immense computing power to global services, and provide the foundational platforms for future development. Our work spans from software to hardware, with key contributions to TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Key responsibilities include evaluating, analyzing, implementing, and integrating SRAMs, custom circuits, and other memory types like multiport register files. You will drive seamless IP integration and ensure proper margins in collaboration with the physical design team.

Work closely with foundries, IP partners, and technology, physical design, and architecture teams to optimize product performance, power, area (PPA), schedule, and reliability in advanced CMOS nodes. You will also lead and support test chip design, execution, and validation for critical circuit IPs.

This role involves designing and building custom circuits at transistor and gate levels to support physical design and PPA optimization. You will also drive the development of a leading-edge technology platform for custom, high-performance ASICs and SoCs, overseeing the entire process from design through manufacturing, packaging, and testing.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required. You should possess a minimum of 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, specifically within advanced nodes like 7nm or below.

Demonstrated experience with SPICE and transistor-level design in advanced nodes is essential. You will need expertise in concurrent optimization across custom circuit/IP and physical design, encompassing Place and Route (PNR) and Static Timing Analysis (STA).

Furthermore, experience in CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics is crucial. Proficiency in scripting or automation using languages such as Tcl, Python, or Perl is also a requirement. A Master's degree or PhD in a relevant field with a focus on computer architecture is preferred.