Join a forward-thinking team dedicated to developing custom silicon solutions that propel Google's direct-to-consumer products. Your contributions will be instrumental in the innovation behind widely-loved products, shaping the next generation of hardware with exceptional performance, efficiency, and integration.

This role offers a unique opportunity to influence the advancement of AI/ML hardware acceleration. You will drive cutting-edge TPU technology crucial for Google's most demanding AI/ML applications. Become part of a pioneering team that creates custom silicon for Google's TPUs, contributing to products used by millions globally. Leverage your design and verification expertise to validate complex digital designs, with a focus on TPU architecture and its integration within AI/ML driven systems.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with advanced capabilities and insights through large-scale, efficient, reliable, and rapid AI and Infrastructure delivery. Our impact spans across Googlers, Google Cloud customers, and billions of users worldwide.

We are the driving force behind Google's groundbreaking innovations. Our teams empower the development of cutting-edge AI models, deliver unparalleled computing power to global services, and provide the foundational platforms for developers building the future. From software to hardware, our contributions shape world-leading hyperscale computing, with key efforts focused on TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Evaluate, analyze, implement, and integrate SRAMs, other memory types (like multiport register files), and custom circuits. Ensure seamless IP integration and manage margins effectively with the physical design team.

Collaborate closely with foundries, IP partners, and the technology, physical design, and architecture teams to optimize products for power, performance, area (PPA), schedule, and reliability in advanced CMOS nodes.

Lead and support test chip design, execution, and validation for critical circuit IPs.

Design and construct custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.

Drive the development of a leading-edge technology platform for custom, high-performance ASICs and SoCs, overseeing the entire lifecycle from design through manufacturing, packaging, and testing.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required.

Minimum of 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, specifically within advanced nodes like 7nm or below.

Proficiency with SPICE and transistor-level design in advanced process nodes.

Experience in concurrent optimization across custom circuit/IP and physical design, encompassing Place and Route (PNR) and Static Timing Analysis (STA).

Familiarity with CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics. Proven experience in scripting or automation using languages such as Tcl, Python, or Perl.

Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture. Experience with scripting languages like Perl, Python, or Tcl is beneficial.

Additional preferred experience includes working with foundry technology files (PDKs), standard cell libraries, metal stacks, and understanding collaterals for front-end and back-end design teams. A strong track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout is desirable.

Understanding of characterization and verification for standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis. Excellent documentation and presentation skills are essential for effective communication with teammates and vendors/partners.