Join Google Cloud's innovative team shaping custom silicon solutions for direct-to-consumer products. You will contribute to next-generation hardware, delivering unparalleled performance and efficiency. This role focuses on advancing AI/ML hardware acceleration, driving cutting-edge TPU technology that powers Google's most demanding applications.

The AI and Infrastructure team is at the forefront of innovation, empowering Google customers with breakthrough capabilities at an unprecedented scale. We deliver AI and Infrastructure solutions with exceptional efficiency, reliability, and velocity to Googlers, Google Cloud customers, and billions of users worldwide.

We are the engine behind Google's groundbreaking innovations. Our teams are responsible for developing advanced AI models, providing immense computing power for global services, and building essential platforms for developers. Our work spans software and hardware, influencing the future of world-leading hyperscale computing, including the development of TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, and systems research.

Evaluate, analyze, implement, and integrate SRAMs, other memory types (such as multiport register files), and custom circuits. Drive effective IP integration and ensure proper margins with the physical design team. Collaborate with foundries, IP partners, and technology, physical design, and architecture teams on advanced CMOS nodes to optimize products for power, performance, area (PPA), schedule, and reliability. Lead and support test chip design, execution, and validation of critical circuit IPs. Design and construct custom circuits at the transistor and gate levels, supporting physical design and power-performance-area optimization. Spearhead the development of a leading-edge technology platform for custom, high-performance ASICs and SoCs, managing the entire process from design through manufacturing, packaging, and testing.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline, or equivalent practical experience, is required. Minimum of 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, particularly with advanced process nodes (e.g., 7nm or below). Proficiency in SPICE and transistor-level design within advanced nodes. Experience in concurrent optimization across custom circuit/IP and physical design, encompassing Place and Route (PNR) and Static Timing Analysis (STA). Demonstrated experience in CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics. Skilled in scripting or automation using languages such as Tcl, Python, or Perl. A Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with a specialization in computer architecture, is preferred. Experience with scripting languages like Perl, Python, or Tcl is beneficial. Familiarity with foundry technology files (PDKs), standard cell libraries, metal stacks, and other relevant features. Understanding of collaterals crucial for front-end and back-end design teams. Proven track record of delivering optimized custom circuits/memories/IPs and PNR blocks for product tapeout. Knowledge of standard cell/SRAM/register file characterization and verification, including power, noise, variation, and IR analysis. Excellent documentation and presentation skills for effective communication with teammates and vendors/partners.