Join a pioneering team at Google Cloud, dedicated to developing cutting-edge custom silicon solutions that power the next generation of direct-to-consumer products and AI/ML hardware acceleration.

You'll have the opportunity to shape innovative TPU (Tensor Processing Unit) technology, contributing to products used by millions worldwide. Your expertise will be crucial in delivering unparalleled performance, efficiency, and integration, driving the future of hardware experiences.

This role is ideal for individuals passionate about advancing AI/ML driven systems and contributing to the essential platforms that enable developers. You will be a key player in a team that redefines computing possibilities, working on everything from software to hardware for world-leading hyperscale computing.

Evaluate, analyze, and implement SRAMs, other memory types, and custom circuits, ensuring seamless IP integration with the physical design team.

Collaborate with foundries, IP partners, and internal teams to optimize products for performance, schedule, and reliability within advanced CMOS nodes.

Drive the design, execution, and validation of critical circuit IPs through test chip development.

Design and construct custom circuits at transistor and gate levels to enhance physical design and power-performance-area optimization.

Contribute to the development of a leading-edge technology platform for custom, high-performance ASICs and SoCs, overseeing the entire process from design through manufacturing, packaging, and testing.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience is required.

Possess at least 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, including experience with advanced nodes (e.g., 7nm or below).

Demonstrated experience with SPICE and transistor-level design, along with concurrent optimization across custom circuits/IP and physical design, including PNR and STA.

Familiarity with CMOS device physics, finfet/GAA/nanosheet architectures, or layout parasitics is essential.

Proficiency in scripting or automation using languages like Tcl, Python, or Perl is expected.

Preferred qualifications include a Master's degree or PhD in a relevant engineering or computer science field, with an emphasis on computer architecture. Experience with foundry technology files, standard cell libraries, and collaterals for design teams is advantageous. A strong track record of delivering optimized custom circuits and PNR blocks, alongside an understanding of characterization and verification, is highly valued.