Join a pioneering team shaping the future of Google's direct-to-consumer products through custom silicon solutions. This role offers a unique opportunity to drive innovation in AI/ML hardware acceleration, particularly with cutting-edge TPU technology powering Google's demanding applications. You'll contribute to products used by millions globally, leveraging your design and verification expertise for complex digital designs.

The AI and Infrastructure team is at the forefront of redefining possibilities, providing AI and Infrastructure at unparalleled scale and efficiency. We empower both internal Googlers and external Google Cloud customers, influencing billions of users worldwide. Our efforts are crucial for groundbreaking AI models, immense computing power for global services, and essential platforms for developers.

We are instrumental in Google's hyperscale computing advancements, focusing on TPU development, Vertex AI for Google Cloud, global networking, data center operations, and systems research.

Evaluate, analyze, and integrate SRAMs, multiport register files, and other custom circuits. Collaborate with the physical design team to ensure optimal IP integration and margins. Partner with foundries, IP partners, and internal teams (technology, physical design, architecture) in advanced CMOS nodes to refine product PPA, schedule, and reliability. Oversee test chip design, execution, and validation for critical circuit IPs. Develop custom circuits at transistor and gate levels to support physical design and power-performance-area optimization. Lead the development of a state-of-the-art technology platform for high-performance ASICs and SoCs, from design through manufacturing and testing.

A Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Minimum of 8 years of experience in circuit design, physical design (RTL-to-GDS), or technology development, including advanced nodes (e.g., 7nm and below). Proficiency in SPICE and transistor-level design within specified nodes. Demonstrated experience in concurrent optimization across custom circuits/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA). Familiarity with CMOS device physics, FinFET/GAA/nanosheet architectures, or layout parasitics, coupled with scripting proficiency in languages like Tcl, Python, or Perl.