Shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role involves developing custom silicon solutions that power Google's most demanding AI/ML applications and contributing to the innovation behind beloved products.

You will play a crucial role in verifying complex digital designs, with a particular focus on TPU architecture and its integration within AI/ML-driven systems. Your expertise will be instrumental in delivering emulation-based prototyping capabilities for ASIC projects, encompassing project compilation, platform management, and issue resolution.

Join a dynamic team at the forefront of redefining AI and Infrastructure. We empower Google customers with breakthrough capabilities and insights through unparalleled scale, efficiency, and reliability. Our efforts fuel groundbreaking innovations, delivering computing power to global services and enabling developers to build the future.

Build and deliver full chip emulation or FPGA prototypes for complex SoC designs to various customer teams, including Software, Firmware, Platform, and Post-Silicon Validation. Influence Design and Verification teams to adopt emulation-friendly model development practices. Spearhead system-level emulation model bring-up, including reset, boot, and bare-metal content or OS execution. Collaborate with Architects, Designers, Software Engineers, and Pre/Post-Silicon Verification Engineers to craft test plans, define coverage strategies, and reproduce failures on emulation platforms. Develop, execute, and debug comprehensive full-chip/SoC tests on emulation platforms. Actively explore and implement novel verification and emulation methodologies.

Requires a Bachelor's degree or equivalent practical experience, coupled with a minimum of 5 years of experience in full-chip/SoC verification, encompassing test definition, creation, execution, and debugging. Demonstrated experience developing full-chip/SoC tests using environments and tools such as ASM, C, C++, Perspec, OS, or drivers is essential. Proficiency with industry-standard emulator technologies (HAPS, Zebu, Veloce, Palladium), including build tools and advanced capabilities like power-aware emulation. Experience with execution and RTL, firmware, or software debugging on hardware emulation platforms (ZeBu Server, Palladium, Veloce) or FPGAs (Xilinx, Altera). Preferred candidates will possess 8 years of full-chip/SoC verification experience, familiarity with EDA debug tools (Verdi, SimVision/Indago, GDB), and programming/scripting skills in C, C++, Python, Perl, or TCL. Understanding of SoC architecture and interfaces (DDR, PCIe), as well as RTL to Emulation/FPGA flows, is also highly desirable.